Duty cycle regulator

ABSTRACT

A duty cycle regulator derives from an input clock of arbitrary duty cycle an output clock having an adjustable duty cycle of similar frequency. The invention comprises a bistable circuit for receiving an input clock pulse and providing the output clock, coupled through a feedback loop to an adjustable delay unit having a delay interval equal to an adjustable fraction of the input clock period. When an input clock pulse is received, the bistable circuit is set giving high signal to the delay unit, which after said delay interval resets the bistable circuit to give a low signal. The delay unit includes two charge pumps alternately feeding and draining electric charges into and from a low-pass filter. The delay interval can be adjusted to a desired duty cycle independent of the input clock frequency, by setting the ratio of electric currents through the two charge pumps.

FIELD OF INVENTION

[0001] The invention relates to the regulation of a clock duty cycle foruse in conjunction with Very Large Scale Integration (VLSI)microelectronic circuits.

BACKGROUND OF THE INVENTION

[0002] In the field of VLSI microelectronic circuits, many digitalsystems require a certain clock duty cycle (i.e. 50/50%, 40/60%) forproper operation. However, such clock duty cycles are not always readilyavailable. A clock with an inappropriate duty cycle may cause thedigital system to fail or force the system to run at a lower clockspeed. Although many digital systems desire a 50/50% duty cycle, not alldigital systems necessarily desire the same clock duty cycle. Dependingon the source of the clock, the duty cycle may not always be known orpredictable. Hence, duty cycle correction is needed.

[0003] One such approach to duty cycle correction is to use aphase-locked loop to synthesize a clock at double the input frequency,and then to divide down by two to obtain a 50/50% duty cycle. Thisapproach requires the building of a phase-locked loop, which is complexin design, large in area, and high in power. This approach also onlylimits the output duty cycle to 50/50%.

[0004] In U.S. Pat. No. 5,317,202, Waizman discloses a 50% duty-cycleclock generator, which is limited to generating only a 50% duty cycleand its implementation complicated.

[0005] In U.S. Pat. No. 5,572,158, Lee et al describe an amplifiercircuit with active duty cycle correction to produce a pre-determinedduty cycle. However, such a circuit uses three operational amplifiers,thus being relatively high in power consumption and large in area.

[0006] In U.S. Pat. No. 5,757,218, Blum describes a circuit and a methodfor signal duty cycle correction, which involves the use of a ringoscillator counter to produce adjustable delays. In order for thisapproach to have sufficient duty cycle resolution, the ring oscillatormust operate at a frequency much higher than the input clock, meaning alarge use of power. Lower operating speeds would mean degradation in theduty cycle resolution.

[0007] In U.S. Pat. No. 5,550,499, Eitrheim describes an adjustable dutycycle clock generator using multiplexers to adjust the delay in a delayline. The problem with this approach is that the amount of delay neededis not known by the circuit and must be determined elsewhere eitherthrough measurement or other dynamic means. This circuit cannotself-correct for the appropriate duty cycle.

[0008] In U.S. Pat. No. 5,617,563, Banerjee et al describe a duty-cycleindependent tunable clock that uses an adjustable delay line inconjunction with a flip-flop. However, the described circuit is limitedby using a fixed delay, once adjusted (by blowing out fuses through alaser), thereby providing a duty cycle for a given adjustment whichdirectly depends on the clock input. Furthermore, the use of blowing outfuses for changing the duty cycle is relatively expensive and demands alarger overall circuit. Once the fuses are set to provide a desired dutycycle for a particular clock frequency, they cannot be changed again tooperate with a different frequency or to obtain a different duty cycle.

[0009] In U.S. Pat. No. 5,477,180, Chen describes a circuit and a methodfor generating a clock signal wherein the duty cycle is adjustedindependent of the input clock frequency by adjusting a bias voltage atthe driver circuit of the output clock, which is driven by the inputclock. This bias voltage is generated by a differential amplifier drivenby two voltage-adjusted inputs using two adjustable tapped resistors. InChen's approach, however, at least one operational amplifier and fourresistors are required resulting in a relatively large circuit area andhigh power. Furthermore, the resulting output clock signal is shaped byan RC time constant giving relatively long rise/fall times, especiallywhen duty cycles far beyond 50/50% are desired. Chen teaches that forduty cycles far beyond 50/50%, a few of the described circuits can becascaded for better rise/fall times. This would require more operationalamplifiers and more resistors, hence larger circuit size and greaterpower consumption. Moreover, there is no provision in Chen's approachfor adjusting the duty cycles ‘on the fly’, i.e. whenever desired by theuser.

[0010] In view of the limitations of the prior art reviewed above, itwould be desirable to provide an economical circuit and method forregulating a steady state clock duty cycle over a relatively wide rangeof selectable duty cycles, without being dependent on an actual inputclock frequency value.

SUMMARY OF THE INVENTION

[0011] An object of this invention is to provide an improved duty cycleregulator that can receive an input clock signal within a certain rangeof frequencies having any arbitrary duty cycle and to output a clocksignal having a pre-selected duty cycle at the same frequency as that ofthe input clock.

[0012] It is another object of the present invention to allow aselection, within limits, of the output clock's duty cycle for a givenrange of operating frequencies, where such selection can be optionallymade as a programmable feature where the duty cycle generated may bechanged ‘on the fly’.

[0013] In accordance with an aspect of the present invention, there isprovided a duty cycle regulator for receiving an input clock signalhaving an input clock period, and an arbitrary input duty cycle, and forderiving from the input clock signal, an output clock signal having apre-selected duty cycle and the same period as the input clock period.The duty cycle regulator includes: clock output means for providing anoutput clock signal, which periodically alternate between a first signallevel and a second signal level; and delay means responsive to theoutput clock signal, for providing a delayed signal to the clock outputmeans, following a transition in the output clock signal from the firstlevel to the second level, after a pre-selected fraction of the inputclock period.

[0014] In an embodiment of the present invention, the clock output meansis switchable between a first and a second state providing said firstand second signal levels respectively. When a transition between low andhigh levels occurs in the input clock signal along a predetermineddirection, the clock output means responds by attaining the first statethereby giving the first output clock level, and thereafter switches tothe second state thereby giving the second output clock level upontermination of said pre-selected fraction of the input clock period.

[0015] In a hardware implementation of the present invention, the clockoutput means can be in the form of a bistable circuit such as areset/set flip-flop circuit switchable between a first and a secondstate. In such an implementation the bistable circuit has a first inputport for receiving an input clock pulse, a second bistable input portand an output clock port for providing said output clock signal. Thedelay means has an input port coupled to said output clock port, and anoutput port coupled to said second bistable input port for providing adelayed signal after a pre-selected fraction of the input clock period,following a switching of the bistable means from the second state to thefirst state. When, in this configuration, an input clock pulse isprovided to the first bistable input port, the bistable means switchesto said first state giving a first output clock level, and thereafterthe delay means provides the delayed pulse to the second bistable inputport, thereby switching the bistable means to the second state andgiving a second output clock level.

[0016] Conveniently the input clock pulse can be derived from the inputclock signal by a clock pulse generator comprising means for derivingfrom the input clock signal a first clock signal, followed by a secondclock signal delayed from the first clock signal. Here the input clockpulse is generated when the first clock signal overlaps with the secondclock signal.

[0017] The pulse generating means can be configured to comprise: atleast one first delay inverter having a first input port adapted toreceive said input clock signal, and a first output port; at least onesecond delay inverter having a second input port coupled to the firstoutput port, and a second output port; and logic means having two inputports coupled to the first and second output ports respectively, saidlogic means providing a logic AND operation to generate said input clockpulse.

[0018] Preferably, the delay means is configured to comprise: duty-cycledetermination means for receiving the output clock signal at the inputport of the delay means, and for generating a corresponding delaycontrol signal; and delay pulse generator means coupled to receive saiddelay control signal and the output clock signal, for providing saiddelayed signal at the output port of the delay means.

[0019] Here, the duty-cycle determination means can be configured tocomprise: a low-pass filter such as a capacitor; first and second chargepumps feeding and draining electric charges into and out of saidlow-pass filter respectively; a charge pump electric charges saidlow-pass filter; and first and second switching means for respectivelyand alternately turning, said first and second charge pumps on and offupon detecting level changes in the output clock signal provided at theinput port of the delay means, whereby the delay control signal isgenerated at the low-pass filter.

[0020] The pre-selected fraction of the input clock period can beadjusted or programmed “on the fly” by setting a predetermined ratio ofelectric currents of the first charge pump relative to the second chargepump.

[0021] The delay pulse generator means can be configured to comprise acurrent-starved inverter having two input ports coupled to receive theoutput clock signal and the delay control signal respectively, and amiddle port for driving a buffer circuit, whereby said delayed pulse isgenerated upon the delay control signal reaching a predeterminedthreshold subsequent to the output clock signal changing to the firstlevel.

[0022] Preferably the duty cycle regulator as defined above furthercomprises sub-harmonic correction means for receiving the input clocksignal and the output clock signal, and for providing a reset signal tothe delay means to prevent the duty cycle regulator from locking into aclock period different from the input clock period. Such sub-harmoniccorrection means can be configured to comprise an edge-triggeredflip-flop circuit having a D-input coupled to receive the output clocksignal, a trigger input coupled to receive the input clock signal, andan output port for providing the reset signal, such that the resetsignal is generated upon detecting a level transition in the input clocksignal simultaneous to the output clock signal being in the secondsignal level thereof. A driver can be included for receiving the resetsignal and applying a corresponding voltage to the low-pass filter.

[0023] One advantage of the present invention is its relatively goodtolerance against variations in the fabrication process, supply voltage(VDD), and temperature. Such tolerance is due to the inherent featurethat the steady state duty cycle is dependent on the matching of thecurrents of the charge pumps, which in turn depends upon the matching ofcurrent mirrors. Since such matching depends on relative rather thanabsolute current values, it can be achieved with relatively goodaccuracy despite variations in fabrication process, supply voltageand/or temperature.

[0024] In accordance with another aspect of the present invention, amethod of duty-cycle regulation is provided for deriving an output clocksignal having a pre-selected duty cycle from an input clock signalhaving an arbitrary duty cycle and an input clock period. This methodcomprises the steps of: receiving the input clock signal; providingoutput clock means for outputting first and second signal levels whenswitched between a first and a second state respectively; switching theoutput clock means to the first state upon detecting a transition in theinput clock signal along a predetermined direction; determining a delayinterval equal to a pre-selected fraction of the input clock periodfollowing the output clock means switching to the first state; andswitching the output clock means to the second state after said delayinterval.

[0025] Preferably this method further comprises the step of generatingan input clock pulse upon said transition in the input clock signalalong said predetermined direction. Such clock input pulse is used toswitch the output clock means to the first state. The delay interval canbe determined by the steps of: providing a low-pass filter forgenerating a delay control signal; providing a first charge pump to feedelectric charges into said low-pass filter; providing a second chargepump to drain electric charges out of said low-pass filter; turning saidfirst and second charge pumps alternately on and off in accordance withthe output clock means switching between the first and second statesrespectively; and marking an interval between the output clock signalchanging to the first level and the delay control signal reaching apredetermined threshold as the delay interval.

[0026] The pre-selected fraction of the input clock period can beadjusted or programmed on the fly by setting a predetermined ratio ofelectric currents of the first charge pump relative to the second chargepump. The output clock signal can be prevented from locking into a clockperiod different from the input clock period by the steps of: detectinga level transition in the input clock signal simultaneous to the outputclock signal being in the second signal level thereof; generating areset signal; and applying a corresponding voltage to the low-passfilter.

BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Exemplary embodiments of the invention will now be furtherdescribed with reference to the drawings in which:

[0028]FIG. 1 illustrates in a top-level block diagram of a duty cycleregulator in accordance with an embodiment of the present invention;

[0029]FIG. 2 illustrates circuit details of the pulse generator meansand the bistable circuit shown in FIG. 1;

[0030]FIG. 3 illustrates in a circuit diagram, the variable delaycircuit of FIG. 1;

[0031]FIG. 4 illustrates in a timing diagram typical signal waveformsduring a normal operation of the duty cycle regulator shown in FIGS. 2and 3;

[0032]FIG. 5 illustrates in a timing diagram signal waveforms during anoperation of the duty cycle regulator in FIGS. 2 and 3, in absence ofsub-harmonic locking correction;

[0033]FIG. 6 illustrates in a timing diagram the effect of usingsub-harmonic locking correction on signal waveforms during an operationof the duty cycle regulator in FIGS. 2 and 3;

[0034]FIG. 7 illustrates in a circuit diagram the charge pumps andswitching means shown in FIG. 3 in accordance with another embodiment ofthe present invention; and

[0035]FIG. 8 illustrates in a circuit diagram an alternative embodimentof charge pumps and switching means shown in FIG. 3 to provide aprogrammable duty cycle.

[0036]FIG. 9 illustrates in a circuit diagram an alternative embodimentfor the design of the delay pulse generator shown in FIG. 3, using anoperational amplifier; wherein same numerals and symbols referencesimilar elements throughout all drawings.

DETAILED DESCRIPTION OF THE INVENTION

[0037]FIG. 1 illustrates in a block diagram a duty cycle regulator 100in accordance with an embodiment of the present invention. In thisembodiment a clock output unit (means) 10 is provided, which has a firstbistable input port 11, and a second bistable input port 12 and anoutput clock port 13. The output port 13 is coupled to an input port 21of a delay unit (means) 20 which has an output port 23 coupled to thesecond bistable input port 12. When the clock output unit 10 receives apulse at its first (set) input port 11, it switches to a first (set)state thereby providing a high level output clock signal CLK_OUT at itsoutput clock port 13. The output clock signal CLK_OUT remains high untilanother pulse is received at its second (reset) input port 12 to switchthe output clock unit 10 back to a second (reset) state, therebyproviding a low level output clock signal at its clock output port 13.

[0038] In this embodiment, the duty cycle regulator 100 operates asfollows. When an input clock pulse S− having a given input clock periodis applied to the bistable input port 11, the clock output means 10 isset, thereby giving a high level at its output port 13. A transition inthis direction in CLK_OUT is detected by the delay unit 20 at its inputport 21, which will then provide a delayed pulse R− at its outport port23 after a certain delay interval equal to a pre-selected fraction ofthe input clock period. This way the duty cycle of CLK_OUT is regulatedin accordance with the value of such pre-selected fraction regardless ofthe frequency of the input clock pulse S−.

[0039] The embodiment shown in FIG. 1 lends itself to an integratedcircuit design. However, other implementations of the same approachdescribed above are also possible, such as by way of using software orfirmware techniques, or even electrical or electronic circuits usingdiscrete components for implementing the two blocks 10 and 20 (shown inFIG. 1).

[0040]FIG. 2 illustrates in a block diagram a duty cycle regulator 100in accordance with a preferred embodiment of the present invention,which is designed to operate using an external (input) clock signalCLK_IN having an arbitrary duty cycle to be received by clock pulsegenerator means 30. The clock pulse generator 30 includes a first seriesof two delay inverters I1 and I2 which receive CLK_IN at a first inputport 33 (I1 input) which provides a delayed first clock signal CLK_DELat a first output port 35 (I2 output). The CLK_DEL signal is then fed toa first of a second series of three delay invertors I3, I4 and I5, whichprovide a further delayed second clock signal CLK_DEL− at a secondoutput port (I5 output). The two clock signals CLK_DEL and CLK_DEL− arethen fed to two respective inputs of logic means N1 in the form of aninverting AND (NAND) gate N1 to generate a negative input clock pulseS−, when CLK_DEL and CLK_DEL− overlap with one another by having a highlevel at the same time.

[0041] In the preferred embodiment of FIG. 2, the clock output means 10is a bistable circuit in the form of an R/S flip-flop composed of NANDgates N2 and N3. As shown in the timing diagram of FIG. 4, this negativepulse S− when applied to the first bistable input port 11 will set theR/S flip-flop causing the output clock signal CLK_OUT at the outputclock port 13 to rise from a logic low level to a logic high level. Thisoutput clock signal is fed back to an input port 21 of the adjustable(or programmable) delay unit 20. When CLK_OUT goes high, the delay unit20 in turn detects a transition in such a direction in CLK_OUT andgenerates a negative delayed pulse R− provided to a second bistableinput port 12 upon termination of a time delay interval, which is apre-selected fraction of the input clock period, causing CLK_OUT to fallfrom high to low. CLK_OUT will remain low until the next negativedelayed clock pulse S− appears at first input port 11, thus completingone full clock cycle. The duty cycle of CLK_OUT depends on the length ofdelay interval that the delay unit 20 introduces between the timeCLK_OUT goes high and the time a negative delayed clock pulse R− isprovided to the second input port 12. In the circuit of FIG. 2, theinverters I1 and I2 provide a buffer and a delay for the external clocksignal CLK_IN to facilitate the operation of the variable delay circuitas will be described further below.

[0042]FIG. 3 illustrates the design of the adjustable delay unit 20according to an embodiment of the present invention. It includes threemajor blocks: a duty cycle determination block 40, delay pulse generatorblock 50, and sub-harmonic correction block 60. Within the duty cycledetermination block 40, two charge pumps 41 (PUMP1) and 42 (PUMP2) arealternately turned on and off by level changes in the output clocksignal CLK_OUT and an inverted output clock signal CLK_OUT−, via firstand second switching means S1 and S2 respectively, together with alow-pass filter 43 (LPF), which in this embodiment has the form of acapacitor. The duty cycle determination block 40 controls a delaycontrol signal in the form of a voltage VCONT, which in turn controlsthe actual delay of the delay pulse generator 50 made up by thecurrent-starved inverter 53 composed of PMOS transistor P1, and NMOStransistors N1 and N2. Within the sub-harmonic correction block 60, anedge-triggered bistable circuit 61, in the form of a D-type flip-flop,eliminates the possibility of the duty cycle regulator locking into asub-harmonic of the input frequency, i.e. any clock period which isdifferent from the input clock period.

[0043] The signals CLK_OUT and CLK_OUT− control the voltage VCONT bycausing one charge-pump 41 to feed (source) and the other 42 to drain(sink) electric charges alternately into and out of the capacitor 43.The ratio of the two respective charge-pump currents is set inaccordance with a desirable ratio of the duration of times that thepumps are turned on and off. For example, if the duty cycle is to be40/60%, then the currents through PUMP1 and PUMP2 will also have 40/60(⅔) ratio respectively. The setting of the charge-pump ratio, therefore,effectively sets the output clock's duty cycle. When the circuitrywithin the duty cycle determination block 40 is in ‘lock’ (it takes sometime for this circuit to achieve a steady state final duty cycle value),the average voltage VCONT should be constant by virtue of theself-regulating low-pass filter 43. On the other hand, if the currentsin PUMP1 and PUMP2 were identical, then the only way VCONT can stayconstant is when CLK_OUT and CLK_OUT− are high for an identical durationof time, hence, implying a 50/50% duty cycle.

[0044] The delay pulse generator 50 includes a current starved inverter53 followed by a buffer B3. This portion of the circuit receives VCONTand CLK_OUT at its input ports 51 and 52 respectively and provides atits middle port 54 a signal DELAY, and then becomes R− the delay unitoutput port 23, which is then fed back as CLK_OUT to the delay unitinput port 21 after passing through the output clock unit 10.

[0045] In operation, when CLK_OUT goes high, the middle port 54 tries togo low. However, since the NMOS transistor N2 is not fully on due to thevalue of VCONT, the fall time of the signal DELAY at the middle port 54of the current-starved inverter is slow when compared to other digitalsignals within the duty cycle regulator system 100. When the signalDELAY goes low below the threshold of buffer B3, R− also goes low,forcing CLK_OUT to go low due to the reset action of the output clockunit 10 of FIG. 2. When fed-back CLK_OUT signal goes low, the signalDELAY is rapidly pulled high by the transistor P1. As there are notransistors in series with the PMOS transistor P1, the signal DELAYeventually pulls high quite rapidly as opposed to when it is beingpulled low. The behavior of the current-starved inverter 53 inconjunction with a delay in the buffer B3 is effectively what determinesthe delay interval marked as the inteval between the time CLK_OUT goeshigh and the time a negative delayed pulse R− is generated at the delayunit output port 23. The buffer delay is constant. The delay caused bythe current-starved inverter is determined by the resistance of the NMOStransistor N2 which in turn is determined by the voltage VCONT from theduty cycle determination block 40.

[0046] The sub-harmonic correction block 60 includes an inverter I6, anedge-triggered flip-flop circuit 61, and a PMOS transistor P3. Theflip-flop circuit 61 has a D-input 63 coupled to receive the outputclock signal CLK_OUT via the inverter I6, and a trigger input 64 coupledto receive the input clock signal CLK_IN and an output port 65 forproviding a reset signal RESET. The signal RESET is generated by theflip-flop circuit 61 upon detecting a positive level transition inCLK_IN simultaneous to CLK_OUT being low.

[0047] Without sub-harmonic correction, the duty cycle regulator 100 mayarrive at a stable state in which the output clock is a sub-harmonic ofthe input clock. This may occur if at power-up, the voltage VCONT isinitially at a relatively very low level. Under normal operations, whenCLK_IN goes high, it is usually expected that CLK_OUT is currently low.However, under sub-harmonic conditions, there are instances where CLK_INis high at the same time as CLK_OUT is high. If this event shall occur,the edge-triggered flip-flop circuit 61 through inverter I6 will cause alow binary level signal RESET− output port 65 of the flip-flop circuit61 to appear, causing a driver 62 in the form of a PMOS transistor P3 topull VCONT up to VDD voltage. When VCONT is at VDD voltage, thecurrent-starved inventor 53 in the delay pulse generator 50 has theleast delay. On the subsequent clock cycle triggered by CLK_IN, RESET−is returned to high and the duty cycle regulator 100 returns to normaloperation. Hence, sub-harmonics are eliminated, under suchcircumstances.

[0048] The inverters I1 and I2 within the clock pulse generator 30 shownin FIG. 2 serve to delay somewhat the rising edge of CLK_OUT withrespect to CLK_IN to facilitate the operation of the sub-harmoniccorrection circuit 60, which samples CLK_OUT on the positive edge ofCLK_IN. If CLK_OUT is sampled as high, then a sub-harmonic is detectedto exist because CLK_OUT's period is greater than one CLK_IN clockcycle. However, if CLK_OUT is sampled as low, then a sub-harmonic isdetected as non-existent, and the sub-harmonic correction circuit 60 iseffectively inactive. To ensure that the sub-harmonic correction circuit60 samples CLK_OUT correctly, some margin is desirable between the timeCLK_IN rises and the time CLK_OUT rises, which is provided by theinverters I1 and I2. Furthermore, the inverter I6 in the sub-harmoniccorrection block 60 shown in FIG. 3 serves a similar purpose in thesense that it further delays the inverted rising edge of CLK_OUT intothe sub-harmonic correction circuit.

[0049]FIG. 4 illustrates the waveforms of the duty cycle regulator undernormal operation. With reference back to FIG. 2, the operation duringnormal conditions will now be explained. In FIG. 4, the input clockCLK_IN is shown to have a 75/25% duty cycle, possibly an undesirableduty cycle for a particular operation.

[0050] For the purpose of illustration, the duty cycle regulator inaccordance with the present invention is shown to be pre-set forcorrecting the duty cycle to 50/50%. As shown in FIG. 2, CLK_DEL is aslightly delayed version of CLK_IN through inverters I1 and I2 whileCLK_DEL− is an even further inverted version of CLK_DEL, delayed throughinverters I3, I4 and I5. At the input of NAND gate N1, there is a briefperiod of time in which both CLK_DEL and CLK_DEL− are high, herebyproviding a negative clock pulse S−. This causes CLK_OUT to go highevery time S− goes low. The duty cycle is then interactively adjusted bythe duty cycle determination block 40 and the delay pulse generator 50.Specifically, when CLK_OUT goes high, PUMP1 in the duty cycledetermination block 40 is turned on, charging up VCONT. At the sametime, DELAY is being pulled low. When DELAY has been pulled below thethreshold voltage of buffer B3, R− goes low, causing CLK_OUT to go lowthrough the R/S flip-flop 10. When CLK_OUT is low, PUMP2 is turned onvia switching means S2, pulling VCONT lower. It is to be noticed that atthe start of the next rising edge of CLK_OUT, VCONT is then lower thanthe previous edge. This is due to the fact that the current duty cycleof CLK_OUT is not high for a sufficient length of time. A lower VCONTwould mean a longer delay in the delay pulse generator 50 inside thedelay circuit 20, causing the next clock cycle of CLK_OUT to be high fora longer time. Utilizing this iterative feedback system, CLK_OUTeventually approaches a 50/50% duty cycle, as shown in FIG. 4. Once itdoes, the voltage VCONT is bounded and its average voltage is constant.The currents through PUMP1 and PUMP2 are equal at this time. Note thatfor illustration purposes, the figure shows that ‘lock’ is achieved inseveral clock cycles. In an actual practical design, this process willtake many more clock cycles.

[0051]FIG. 5 illustrates in a timing diagram what might happen should asub-harmonic correction block 60 not be included in the design of thedelay circuit 20. Here CLK_OUT is noted to be at half the frequency ofCLK_IN with a falling edge just past the negative clock pulse of S−.This circuit is in ‘lock’ condition because VCONT has reached a steadystate average voltage.

[0052]FIG. 6 illustrates that with the sub-harmonic correction block 60added in, at the rising edge of CLK_IN, this block detects that CLK_OUTis still high. This causes the output RESET− of the edge-triggeredflip-flop 61 to go low, pulling VCOLNT to VDD. On the next clock cycle,RESET− is high again and the system is back under normal operationalconditions.

[0053] In FIG. 7, typical circuit details as readily available in theart are illustrated for the charge pumps PUMP1 and PUMP2 and theswitching means S1 and S2 shown in FIG. 3 within the duty cycledetermination block 40. In FIG. 7, the charge pumps PUMP1 and PUMP2 andthe switching means S1 and S2 are shown as part of a charge-pump branch71, where the currents flowing through PUMP1 and PUMP2 are controlled bycurrent mirror branches 72, and a current reference branch 73.

[0054] In alternative embodiments, the charge-pump currents can be madeto be adjustable or programmable on the fly by having multiple currentbranches in parallel within the charge-pump branch 71 as illustrated inFIG. 8. In this fashion, the duty cycle can be changed by selectivelyturning on and off particular combinations of these current branchesthrough the sink and source signals EN_SNK0, 1, 2, etc. and EN_SNK0, 1,2, etc. as shown in FIG. 8.

[0055] In alternative embodiments, the charge pumps 41 and 42 can beimplemented in any one of a number of different ways, including astandard push-pull charge-pump, and many other charge-pump designs thatexist in current open literature without departing from the scope ofthis invention. Similarly many design variations are available in theart for implementing the edge-triggered flip-flop 61 in alternativeembodiments.

[0056] Variations in the design of the delay pulse generator 50 shown inFIG. 3 for making use of the control voltage VCONT are also available inthe art. One such design is shown in FIG. 9 which uses an operationalamplifier 90 in a voltage follower configuration. In this configuration,CLK_OUT is applied to the delay unit input port 21 and VCONT to thevoltage follower input port 91, wherein the delayed pulse R− isgenerated at the delay unit output port 23.

[0057] Although the present invention has been described with particularreference to certain preferred embodiments thereof, numerous variationsand particular adaptations can be applied to the particular embodimentsof the invention described above, without departing from the spirit andscope of the invention, which is defined in the claims.

[0058] Furthermore, the above embodiments are described with aparticular reference to a hardware implementation using integratedcircuit design, the invention as claimed can be put to practice by aperson skilled in the art via a firmware or a software implementation ofits various functional blocks as described above and defined in theclaims.

What is claimed is:
 1. A duty cycle regulator for deriving an outputclock signal having a pre-selected duty cycle from an input clock signalhaving an input clock period, said duty cycle regulator comprising: a)bistable means having an output clock port for providing said outputclock signal, and further having first and second bistable input portsfor switching said bistable means between a first state and a secondstate thereof; and b) delay means having an input port coupled to saidoutput clock port, and an output port coupled to said second bistableinput port for providing a delayed pulse after a pre-selected fractionof the input clock period, following a switching of the bistable meansfrom the second state to the first state; such that when an input clockpulse is provided to the first bistable input port, the bistable meansattains said first state giving a first output clock level, andthereafter the delay means provides the delayed pulse to the secondbistable input port, thereby switching the bistable means to the secondstate giving a second output clock level.
 2. A duty cycle regulator asdefined in claim 1, wherein said bistable means is a Reset/Set flip-flopcircuit.
 3. A duty cycle regulator as defined in claim 1, furthercomprising clock pulse generator means for receiving said input clocksignal, said clock pulse generator means having an output port coupledto the first bistable input for providing said input clock pulse upondetecting a transition in the input clock signal along a predetermineddirection.
 4. A duty cycle regulator as defined in claim 3, wherein saidclock pulse generator means comprises means for deriving from said inputclock signal a first clock signal followed by a second clock signaldelayed from said first clock signal, and wherein the input clock pulseis generated when said first clock signal overlaps with said secondclock signal.
 5. A duty cycle regulator as defined in claim 4, whereinsaid clock pulse generator means comprises: i) at least one first delayinverter having a first input port adapted to receive said input clocksignal, and a first output port; ii) at least one second delay inverterhaving a second input port coupled to the first output port, and asecond output port; and iii) logic means having two input ports coupledto the first and second output ports respectively, said logic meansproviding a logic AND operation to generate said input clock pulse.
 6. Aduty cycle regulator as defined in claim 1, wherein said delay meanscomprises: i) duty-cycle determination means for receiving the outputclock signal at the input port of the delay means, and for generating acorresponding delay control signal; and ii) delayed pulse generatormeans coupled to receive said delay control signal and the output clocksignal, for providing said delayed pulse at the output port of the delaymeans.
 7. A duty cycle regulator as defined in claim 6, wherein saidduty-cycle determination means comprises: i) a low-pass filter; ii) afirst charge pump feeding electric charges into said low-pass filter;iii) a second charge pump draining electric charges out of said low-passfilter; and iv) first and second switching means for respectively andalternately turning, said first and second charge pumps on and off uponlevel changes in the output clock signal provided at the input port ofthe delay means, whereby the delay control signal is generated at thelow-pass filter.
 8. A duty cycle regulator as defined in claim 7,wherein said pre-selected fraction of the input clock period isadjustable by setting a predetermined ratio of electric currents of thefirst charge pump relative to the second charge pump.
 9. A duty cycleregulator as defined in claim 7, wherein said low-pass filter is acapacitor.
 10. A duty cycle regulator as defined in claim 7, wherein thedelayed pulse generator means comprises a current-starved inverterhaving two input ports coupled to receive the output clock signal andthe delay control signal respectively, and a middle port for driving abuffer circuit, whereby said delayed pulse is generated upon the delaycontrol signal reaches a predetermined threshold subsequent to theoutput clock signal changing to the first level.
 11. A duty cycleregulator as defined in claim 7, wherein the delayed pulse generatormeans comprises a voltage follower circuit driven by the delay controlsignal.
 12. A duty cycle regulator as defined in claim 6, furthercomprising sub-harmonic correction means for receiving the input clocksignal and the output clock signal, and for providing a reset signal tothe delay means to prevent the duty cycle regulator from locking into aclock period different from the input clock period.
 13. A duty cycleregulator as defined in claim 12, wherein the duty cycle regulatorcomprises an edge-triggered flip-flop circuit having a D-input coupledto receive the output clock signal, a trigger input coupled to receivethe input clock signal, and an output port for providing the resetsignal, such that the reset signal is generated upon detecting a leveltransition in the input clock signal simultaneous to the output clocksignal being in the second signal level thereof.
 14. A duty cycleregulator as defined in claim 13, wherein the sub-harmonic correctionmeans further comprises a driver for receiving the reset signal andapplying a corresponding voltage to the low-pass filter.
 15. A dutycycle regulator as defined in claim 1, wherein said delay meanscomprises: i) a low-pass filter; ii) a first charge pump feedingelectric charges to said low-pass filter; iii) a second charge pumpdraining electric charges out of said low-pass filter; and iv) first andsecond switching means for respectively and alternately turning, saidfirst and second charge pumps on and off upon level changes in theoutput clock signal provided at the input port of the delay means;whereby said pre-selected fraction of the input clock period isadjustable by setting a predetermined ratio of electric currents of thefirst charge pump relative to the second charge pump.
 16. A duty cycleregulator for deriving an output clock signal having a pre-selected dutycycle from an input clock signal having an input clock period, said dutycycle regulator comprising: a) delay means for providing a delayed pulseafter a pre-selected fraction of the input clock period, following atransition in the input clock signal along a predetermined direction;and b) clock output means responsive to the input clock signal and tothe delayed pulse, for providing the output clock signal; wherein saidoutput clock signal has a first signal level upon said transition in theinput clock signal along said predetermined direction, and a secondsignal level after the delayed pulse.
 17. A duty cycle regulatorcomprising: a) clock output means for receiving an input clock signalhaving an input clock period, and providing an output clock signalalternating between a first signal level and a second signal level; andb) delay means responsive to the output clock signal for providing adelayed pulse to the clock output means following a transition in theoutput clock signal from the first level to the second level, after apre-selected fraction of the input clock period; wherein the clockoutput means responds to a transition in the input clock signal along apredetermined direction by attaining the first level, and thereafterchanges to the second level upon expiry of said pre-selected fraction ofthe input clock period.
 18. A duty cycle regulator as defined in claim16, wherein said clock output means is switchable between a first and asecond state providing said first and second signal levels respectively.19. A duty cycle regulator as defined in claim 16, wherein saidpre-selected fraction of the input clock period is adjustable on thefly.
 20. A duty cycle regulator as defined in claim 17, wherein thedelay means comprises: i) duty-cycle determination means for generatinga delay control signal in response to the output clock signal; and ii)delayed pulse generator means for providing the delayed pulse to theclock output means in response to said delay control signal and to theout put signal